This application claims priority to S.N. 99401390.2, filed in Europe on Jun. 9, 1999.
This invention generally relates to microprocessors, and more specifically to improvements in shared access memory circuits, systems, and methods of making.
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for""specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of processors, such as for example, but not exclusively, digital signal processors.
In accordance with a first aspect of the invention, there is provided a digital system having a memory circuit that can be accessed by several requestor circuits. A scheduling circuit is connected to the requester circuits and is operable to sequentially schedule memory accesses to the memory circuit. A selection circuit is connected to one of the requester circuits and to the output of the scheduling circuit.
Priority circuitry is provided for comparing a first priority for the first requestor and a second priority for the second requestor. The priority circuitry is controllably connected to the selection circuit, such that both the first requestor circuit and the second requestor circuit can sequentially access the memory circuit when the priority circuitry indicates a first relative priority state between the first priority and the second priority and such that the first requestor circuit has exclusive access to the memory circuit when the priority circuitry indicates a second relative priority state.
According to another aspect of the present invention, there is a first priority register for holding the first priority for the first requestor circuit and a second priority register for holding the second priority for the second requestor. The first priority register and the second priority register can be changed in response to a write transaction by at least one of the requestor circuits.
According to another aspect of the present invention, there is a clock circuit connected to the second requestor and to the memory circuit. The memory circuit operates synchronously with the clock circuit when the priority circuitry indicates the first relative priority state exists. The memory circuit operates in an asynchronous manner when the priority circuitry indicates the second relative priority state.
According to another aspect of the present invention, a method of operating a digital system having a memory circuit that is shared by a plurality of requester circuits each having a priority level is provided, comprising the steps of: (a) setting the priority levels to have a first set of relative values, (b) sharing access to the memory circuit between the plurality of requestor circuits while the priority levels have the first set of relative values, (c) setting the priority levels to have a second set of relative values, and (d) limiting access to the memory circuit to only a first requestor of the plurality of requesters while the priority levels have the second set of relative values, such that the first requestor has faster memory access during limited access.